Analytical Modeling of SRAM Dynamic Stability
- 1 November 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2006 IEEE/ACM International Conference on Computer Aided Design
- No. 10923152,p. 315-322
Abstract
In this paper, for the first time, a theory for evaluating dynamic noise margins of SRAM cells is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closed-form expression. The key innovation involves using the methods of nonlinear system theory in developing the model. It is shown that when a transient noise of given magnitude affects a sensitive node of a cell, the bi-stable, feedback-driven nature of the cell determines whether the noise will be suppressed or will evolve to eventually flip state. The specific formal and quantitative result is a closed-form expression that can be used to predict whether a cell flip will occur for a noise signal with specific characteristics, and for a given SRAM cell design. Experiments show excellent match between the analytical prediction and the SPICE simulation resultsKeywords
This publication has 13 references indexed in Scilit:
- Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell ProcessorIEEE Journal of Solid-State Circuits, 2005
- Closed-Form Simulation and Robustness Models for SEU-Tolerant Design2005
- Variability in sub-100nm SRAM designs2005
- Basic mechanisms and modeling of single-event upset in digital microelectronicsIEEE Transactions on Nuclear Science, 2003
- Nonlinear Control Systems2003
- A model for transient fault propagation in combinatorial logic2003
- Interconnect and circuit modeling techniques for full-chip power supply noise analysisIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1998
- Algorithms for transient three-dimensional mixed-level circuit and device simulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Two-Dimensional Simulation of Single Event Indujced Bipolar Current in CMOS StructuresIEEE Transactions on Nuclear Science, 1984