A hardware implementation for real-time lane detection using high-level synthesis
Authors:
- 1 January 2018
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Abstract
Lane detection plays an important role in advanced driving assistance systems (ADAS). In this paper, a hardware implementation of a real-time lane detection is developed using the Xilinx's Zynq-7000 APSoC platform. The proposed algorithm of lane detection uses the Hough transform, which is necessary in our implementation but causes a performance bottleneck. The overlapping pipeline architecture is adopted so that latency and stage memory are minimal. While running at 100 MHz, the implemented hardware can achieve a speed performance of 130 frames per second, for a frame resolution of 480×270. Video streams of actual street conditions are used to test the system. From the test results, accuracy of lane detection is found to be satisfactory.Keywords
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