Qualification of Hardware Description Language Designs for Safety Critical Applications in Nuclear Power Plants

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Abstract
FPGA-based intelligent hardware modules are increasingly being used in safety systems of nuclear power plants. Qualification of these modules as per safety standards such as IEC 62566/60880 and IEEE-7.4.3.2-2010 needs considerable effort. Many of the safety standards demand high rigour in verifying that designs of these modules meet the design intent. Use of Hardware Description Languages such as VHDL or Verilog makes the process of code review and verification difficult due to the complex non-sequential semantics of these languages. It is now recognized that formal verification offers a complementary approach to conventional verification. Formal verification tools perform analysis of designs based on language semantics to prove/refute their functional correctness. In this paper, we present the architecture of a formal verification tool for VHDL designs, and our experience of using this tool on VHDL designs in nuclear applications.
Funding Information
  • Board of Research in Nuclear Sciences (2008/36/14–BRNS/426)