D3TA: 38.9TOPS/W Transformer Accelerator with Dual-Port 3T-eDRAM Digital Compute-in-Memory Using HyperAttention and Triple-Sparsity-Handling
Authors:
- 8 September 2025
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 121-124
Abstract
This paper presents D3TA that accelerates transformers with high system performance. It introduces three key features: 1) HyperAttention (HA) that supports maximum pipelining in memory to minimize the external memory access (EMA) and increase CIM utilization, 2) triple sparsity handling CIM engine that skips redundant near-zero values for energy and latency reduction, and 3) high throughput Dual-port 3T-eDRAM Digital CIM (D3CIM) macro with charge-recycling (CR) and bit-parallel dual radix-4 booth (BPDB) MAC tree group to increase energyand area-efficiency. The D3TA achieves $2.6 \times$ latency reduction in BERT-Base with $2.0 \times$ EMA reduction and 1.28-to-9.75 $\times$ higher system FoM than previous works.
Keywords
Funding Information
- IITP (2022-0-01037)
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