Hybrid-orientation technology (HOT): opportunities and challenges
Authors:
- J.H. StathisJSJ.H. Stathis
- A.I. ChouACA.I. Chou
- E. GusevEGE. Gusev
- J.A. OttJOJ.A. Ott
- L.E. BurnsLBL.E. Burns
- M.V. FischettiMFM.V. Fischetti
- Meikei IeongMIMeikei Ieong
Top Cited Papers
- 24 April 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 53 (5) , 965-978
Abstract
At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.Keywords
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