Manufacturing challenges and method of fabrication of on-chip capacitive digital isolators
Authors:
- 1 January 2007
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 1523553X,p. 1-4
Abstract
A robust and innovative method of fabrication of on-chip capacitive digital isolators integrated in a high precision analog CMOS process is presented in this paper. Several dielectric materials such as TEOS, HDP, silicon nitride, silicon oxynitride, with different film stresses were evaluated for this capacitor in order to achieve the high breakdown voltage (RMS and surge) requirements of the isolation capacitor while ensuring wafer manufacturability. Impact of various integration schemes and combinations of the dielectric layers on the capacitor breakdown voltage performance along with a package and wafer-level reliability assessment of these integration schemes is discussed.Keywords
This publication has 1 reference indexed in Scilit:
- Integrated transformer-coupled isolationIEEE Instrumentation & Measurement Magazine, 2003