Low-Power Low-Latency Data Allocation for Hybrid Scratch-Pad Memory
Authors:
- 5 August 2014
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Embedded Systems Letters
- Vol. 6 (4) , 69-72
Abstract
This letter aims at developing new memory architecture to overcome the daunting memory wall and energy wall issues in multicore embedded systems. We propose a new heterogeneous scratch-pad memory (SPM) architecture that is configured with SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms: a dynamic programming (MDPDA) and a genetic algorithm (AGADA) to allocate data to different memory banks, therefore, reducing memory access cost in terms of power consumption and latency. Extensive experiments are performed to show the merits of the hybrid SPM memory architecture and the effectiveness of the proposed algorithms.Keywords
Funding Information
- Open Research Project of the State Key Laboratory of Industrial Control Technology (ICT1441)
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