Implementation of AES Algorithm using Verilog

Authors:
  • GSGanesh Gopal Shet
    Ganesh Gopal Shet
  • JVJamuna V.
    Jamuna V.
  • SSShravani S.
    Shravani S.
  • NGNayana H. G.
    Nayana H. G.
  • PSPramod Kumar S.
    Pramod Kumar S.
Open Access
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Abstract
Cryptography is very important now-a-days for data security and integrity as the ecommerce and internet applications has increased. But, it has least importance in many cases because of extra memory and other requirements needed for the implementation. The main aim of this work is to implement Advanced Encryption Standard (AES) Encryption using Verilog. To protect data like electronics, cryptographic algorithms are used. The digital information can be encrypted and decrypted by the block cipher of AES algorithm. It can be implemented with the key length 128, 192, 256 bits. Each round of encryption associated with delay can be reduced by AES parallel design.