Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 Transistors

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Abstract
Low-power transistors based on two-dimensional (2D) semiconductors require ultrathin gate insulators, whose atomic layer deposition (ALD) has been difficult without adequate surface preparation. Here, we achieve sub-1 nm equivalent oxide thickness (EOT) on monolayer MoS2 using HfO2 and a simple, commonly available Si seed. We first investigate six seed layer candidates (Si, Ge, Hf, La, Gd, Al2O3) and find that only Si and Ge cause no measurable damage to the MoS2. With these, we build monolayer MoS2 transistors using ALD of HfO2 top-gate dielectric and find that the Si seed provides the better, low-hysteresis interface. The thickness of this interfacial layer also controls the threshold voltage, enabling normally-off, well-behaved transistors. The thinnest gate stack reached low EOT ≈ 0.9 nm with low leakage (2) and ∼80 mV/dec subthreshold swing at room temperature. This represents a simple top-gate dielectric deposition approach, achievable within many common nanofabrication facilities.
Funding Information
  • Defense Advanced Research Projects Agency
  • National Research Foundation of Korea (NRF-2022 R1A2C4002559)
  • Stanford University
  • Semiconductor Research Corporation
  • Institute for Basic Science (IBS-R026-D1)
  • Natural Sciences and Engineering Research Council of Canada

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