ERAVC: Enhanced reliability aware NoC router
Authors:
- 1 March 2011
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 19483287,p. 1-6
Abstract
The continuing advances in processing technology result in significant decreases in the feature size of integrated circuits. This shrinking leads to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) are poised to address the demands for high bandwidth communication among processing elements. The structural redundancy inherited in NoC-based design can be exploited to improve reliability and compensate for the effects of failures in digital systems. In this paper, we propose an enhanced fault tolerant micro-architecture for NoC routers. The proposed router supplies dynamic virtual channel allocation using Unified Buffer Structure (UBS) and History Aware Free-slot Tracker (HAFT). Plus, to reduce the associated performance costs of retransmissions in the case of failure, the proposed router employs a high-performance fault tolerant control flow, handling both transient and permanent faults without extra retransmission buffer requirements. Experimental results show a significant improvement in reliability as well as decreases in the average latency and energy consumption.Keywords
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