Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits
Authors:
- 1 December 2013
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 83-88
Abstract
This paper presents several Schmitt trigger logic gates with enhanced noise immunity using variable threshold voltage technique for sub-threshold voltage operation. The proposed logic gates are based on buffer design using dynamic threshold voltage MOS (DTMOS) for low power operation (V DD =0.4V). Our solution dramatically improves noise immunity of logic gates with much less switching power consumption and significant area reduction compared with CMOS Schmitt triggers at the expense of slight increase in delay. The proposed noise immune gate design scheme is verified with an example digital circuit.Keywords
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