A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization
Authors:
- F. RezziFRF. Rezzi
- I. BiettiIBI. Bietti
- M. CazzanigaMCM. Cazzaniga
- R. CastelloRCR. Castello
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (12) , 1987-1999
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- A CMOS continuous-time G/sub m/-C filter for PRML read channel applications at 150 Mb/s and beyondIEEE Journal of Solid-State Circuits, 1997
- An EPRML digital read/write channel IC1997
- Integrated continuous-time filter design - an overviewIEEE Journal of Solid-State Circuits, 1994
- Tunable BiCMOS continuous-time filter for high-frequency applicationsIEEE Journal of Solid-State Circuits, 1992
- Design of a 15-MHz CMOS continuous-time filter with on-chip tuningIEEE Journal of Solid-State Circuits, 1991
- Implementation of PRML in a rigid disk driveIEEE Transactions on Magnetics, 1991
- A 4-MHz CMOS continuous-time filter with on-chip automatic tuningIEEE Journal of Solid-State Circuits, 1988
- High-bandwidth control of the head-positioning mechanism in a Winchester disk driveIEEE Control Systems Magazine, 1987
- Application of Probabilistic Decoding to Digital Magnetic Recording SystemsIBM Journal of Research and Development, 1971
- Application of Partial-response Channel Coding to Magnetic Recording SystemsIBM Journal of Research and Development, 1970