A high gain 107 GHz amplifier in 130 nm CMOS
Authors:
- 1 September 2011
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 08865930,p. 1-4
Abstract
A systematic method to design high gain amplifiers at frequencies close to the fmax of the transistors is introduced. This approach finds the optimum termination conditions to reach the maximum achievable gain of the device. Using this technique in a standard 130 nm CMOS process, we design and implement a 107 GHz amplifier with a gain of 12.5 dB, PAE of 4.4%, and saturated output power of >;2.3 dBm, consuming 31 mW from a 0.95 V supply.Keywords
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