New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
Authors:
- 1 June 2018
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 41-42
Abstract
We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP-3 AI core to achieve high versatility, high performance, and low latency DNN processing. The core also features narrow bit-width streaming data exchange mechanism between the two units. Not only basic 16b FP but also binarized DNN inference computations are supported.Keywords
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