Optimized synchronous rectification stage for low output voltage (3.3 V) DC/DC conversion
Authors:
- J. SebastianJ. Sebastian
- J. UcedaJUJ. Uceda
- F. AldanaFAF. Aldana
- 1 June 1994
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2, 902-908
Abstract
A new strategy to obtain low output voltage (3.3 V) is presented in this paper. The output stage is optimized to minimize losses in the self-driven synchronous rectifiers, by means of a fixed frequency, fixed duty cycle (0.5) driving waveform. The output voltage is controlled by a high switching frequency preregulator. This preregulator can be removed if input voltage variation is low. Very high efficiency (93%) has been obtained in an actual prototype (3.3 V and 20 A) of the optimized SR stage.Keywords
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