A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI
Authors:
- 29 February 2016
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 63 (9) , 858-862
Abstract
Resilient design is a promising approach to mitigate the performance losses resulting from process, voltage, and temperature variations and benefits from average-case path activity. Many such design techniques rely on error-detecting latches (EDLs) to identify timing errors. This brief presents a novel low-power low-area EDL that achieves 31.8% less energy consumption, 15.8% less leakage, and 35.4% less area compared with the most efficient previous designs, reducing the overhead and thereby increasing the potential benefits of resilient designs.Keywords
Funding Information
- Qualcomm
- CAPES and CNPq (Brazil)
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