Half-swing clocking scheme for 75% power saving in clocking circuitry
Authors:
- H. KojimaHKH. Kojima
- S. TanakaSTS. Tanaka
- K. SasakiKSK. Sasaki
- 1 April 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 30 (4) , 432-435
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
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- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logicIEEE Journal of Solid-State Circuits, 1990
- Cascode voltage switch logic: A differential CMOS logic family1984