Planar process for 8-µm period bubble devices using polyimide resin
Authors:
- H. NishidaHNH. Nishida
- N. TsumitaNTN. Tsumita
- N. KoyamaNKN. Koyama
- H. NozawaHNH. Nozawa
- Y. SugitaYSY. Sugita
- 1 March 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Magnetics
- Vol. 18 (2) , 753-758
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- 256 kbit bubble memory chip fabrication and characterizationJournal of Applied Physics, 1979
- Planar multilevel interconnection technology employing a polyimideIEEE Journal of Solid-State Circuits, 1978
- A 300 kbit bubble memory chip with planar structureJournal of Applied Physics, 1978
- Peel Test for Determining the Adhesion of Electrodeposits on Metallic Substrates1978
- A New Transistor with Two‐Level Metal ElectrodesJournal of the Electrochemical Society, 1977
- 68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum featuresIEEE Transactions on Magnetics, 1976
- A Novel Planar Multilevel Interconnection Technology Utilizing PolyimideIEEE Transactions on Parts, Hybrids, and Packaging, 1973
- Fabrication of large bubble circuitsIEEE Transactions on Magnetics, 1973
- CRITICAL THICKNESS AND PERPENDICULAR ANISOTROPY OF EVAPORATED PERMALLOY FILMS WITH STRIPE DOMAINSApplied Physics Letters, 1967