Logicmark: A Logical-Level Watermarking Approach for Secure Ownership Verification in Hardware Designs

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Abstract
Hardware designs that undergo commercialization are susceptible to various threats such as sabotage, theft, and counterfeiting. Consequently, malicious individuals can easily gain access to the circuits, make slight modifications, and claim the designs as their own. These actions have a detrimental impact on chip designers, leading to financial losses and market share reduction for manufacturers. The proposed method introduces a novel approach for embedding hardware watermarks within circuits to establish ownership and ensure integrity. Initially, a logo is created and assigned a unique code using a predefined algorithm. This code is then hashed using the SHA3 algorithm to produce SHA3-logo. To embed the watermark, various inputs are applied and their corresponding outputs are compared to the SHA3-logo code, with the input-output pair showing the least discrepancy chosen for embedding. XOR gates are introduced for bits differing from SHA3-logo, with the watermark activator facilitating alignment. The findings illustrate the effectiveness of the approach in ensuring ownership and integrity. To assess hardware overhead, standard benchmark circuits were employed, revealing a maximum delay overhead of 3.19% and a maximum area overhead of 4.67%. Importantly, the proposed method did not incur any additional power consumption overhead for the circuit in FPGA technology.

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