Intrinsic speed limit of negative capacitance transistors

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Abstract
The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the response of the semiconductor channel in a ferroelectric negative capacitance transistor. The standard Landau-Khalatnikov equation approximates the slow, diffusive limit of the classical equation of motion. Therefore, using it to predict the response speed is unphysical. After extracting the damping and kinetic inductance from THz spectroscopy data, we simulate the full classical equation of motion and analyze the delay. We find that for doped hafnium oxides, the intrinsic delay is around 270 fs, far less than what is required for digital logic.
Funding Information
  • Berkeley Center for Negative Capacitance Transistors

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