A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases
Authors:
- I.S. HsuIHI.S. Hsu
- T.K. TruongTTT.K. Truong
- L.J. DeutschLDL.J. Deutsch
- I.S. ReedIRI.S. Reed
- 1 June 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 37 (6) , 735-739
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- A Fast VLSI Multiplier for GF(2m)IEEE Journal on Selected Areas in Communications, 1986
- VLSI Architectures for Computing Multiplications and Inverses in GF(2m)IEEE Transactions on Computers, 1985
- A VLSI Design of a Pipeline Reed-Solomon DecoderIEEE Transactions on Computers, 1985
- Bit-serial Reed - Solomon encodersIEEE Transactions on Information Theory, 1982