More than moore and beyond CMOS: New interconnects schemes and new circuits architectures

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Abstract
Interconnect dimensions and CMOS transistor feature sizes approach their physical limits. Therefore, scaling will no longer be the sole contributor to performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “More than Moore” and CMOS replacement “beyond CMOS” will be explored. This paper focuses on technology level trends, where it presents “More than Moore”: new interconnect schemes (3D, NoC, optical, wireless), and “Beyond CMOS”: new interconnect schemes (CNT). Moreover, we introduce the recent trends in 3D FPGA, Memory, processors, and NoC architectures 3D integration results in better performance than 2D. Using 3D-FPGA instead of 2D-FPGA results in reduction in interconnect delay, length and hence improved performance and speed. Using 3D-Memory instead of 2D-Memory provides better Bandwidth and less power consumption. Using 3D-Microprocessor instead of 2D-Microprocessor is increasing number of cores while reducing area and improves latency, and bandwidth. Using 3D-NoC instead of 2D-NoC enhances the routing algorithms and improves performance.