A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC
Authors:
- H. RansijnHRH. Ransijn
- P. O'COnnorPOP. O'COnnor
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (10) , 1345-1353
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- A PLL-based 2.5-Gb/s GaAs clock and data regenerator ICIEEE Journal of Solid-State Circuits, 1991
- A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chipIEEE Journal of Solid-State Circuits, 1989
- Fully integrated Gbit/s clock recovery circuit in GaAs1988
- 4 Gbit/s GaAs MESFET laser-driver ICElectronics Letters, 1986
- A self correcting clock recovery curcuitJournal of Lightwave Technology, 1985
- Delay-and-multiply timing recovery circuit for lightwave transmission systems using NRZ format1985
- A monolithic multigigabit/second DCFL GaAs decision circuitIEEE Electron Device Letters, 1984
- A 50 MHz phase- and frequency-locked loopIEEE Journal of Solid-State Circuits, 1979
- Frequency Detectors for PLL Acquisition in Timing and Carrier RecoveryIEEE Transactions on Communications, 1979
- Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color TelevisionProceedings of the IRE, 1954