Automated Generation of Benchmarks for Falsification of STL Specifications

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Abstract
Falsification, whose aim is to detect unsafe behaviors of cyber-physical systems (CPS) that violate signal temporal logic (STL) specifications, has been actively investigated in the past decade. Although numerous falsification approaches have been proposed, the falsification community suffers from a shortage of benchmarks that hinders a thorough assessment of those falsification approaches. In this paper, we bridge this gap by proposing an automated approach for generating falsification benchmarks. Our approach is data-driven: firstly, we generate different time-variant traces (acting as system output traces) that satisfy a given STL specification, and we associate these with corresponding system input traces; then, we use these input and output traces to train an LSTM model that generalizes them. These models can serve as benchmarks for assessing falsification approaches against the given specification. In the experimental evaluation, we validate the generated models by measuring their ability to differentiate the performance of different falsification approaches. Our generated models expose strengths and weaknesses of all the considered falsification approaches, which was not achieved by benchmarks currently used in the falsification community. These results demonstrate the usefulness of our approach and can potentially push forward subsequent research in falsification.
Funding Information
  • Japan Society for the Promotion of Science (JSPS) Kakenhi (JP23H03372, JP23K16865)
  • Engineerable AI Techniques for Practical Applications of High-Quality Machine Learning-Based Systems Project, JST-Mirai (JPMJMI20B8)
  • Japan Society for the Promotion of Science (JSPS) Kakenhi (JP23H03372)

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