Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
- 1 June 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (6) , 2648-2652
Abstract
In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA FET fabrication. Consequently, the thickness of channel and the interchannel space becomes variable depending on the NS width, since the etch time must be determined by the widest channel within a wafer. It results in a channel width dependence of gate work function, gate-to-drain capacitance, and channel interfacial property as well as the electrostatic gate controllability. The electrical characteristic behavior of stacked-GAAFETs induced by these effects was thoroughly investigated through process-based 3-D technology computer-aided design (TCAD) device simulation along with a transmission electron microscopy (TEM) and an energy-dispersive spectroscopy (EDS) analyses. The results confirm that width-dependent effects should be taken into account when fabricating and compact modeling the stacked-GAAFETs with various NS widths which are required for logic and static random access memory (SRAM) applications.Keywords
This publication has 12 references indexed in Scilit:
- Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization2018
- Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET2017
- Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates2016
- Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond2015
- (Invited) Selective Etch of Si and SiGe for Gate All-Around Device ArchitectureECS Transactions, 2015
- Vertical GAAFETs for the Ultimate CMOS ScalingIEEE Transactions on Electron Devices, 2015
- (Invited) Si, SiGe, Ge, and III-V Semiconductor Nanomembranes and Nanowires Enabled by SiGe EpitaxyECS Transactions, 2010
- Germanium for advanced CMOS anno 2009: a SWOT analysis2009
- FinFET-based SRAM design2005
- Isotropic etching of SiGe alloys with high selectivity to similar materialsMicroelectronic Engineering, 2004