Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures
Authors:
- C. ChengCCC. Cheng
- K.K. ParhiKPK.K. Parhi
- 16 October 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Signal Processing
- Vol. 54 (11) , 4419-4434
Abstract
Cyclic convolution is a widely used operation in signal processing. In very large-scale integration (VLSI) design, it is usually implemented with systolic array and distributed arithmetic; however, these implementation designs may not be fast enough or use too much hardware cost when the convolution length is large. This paper presents a new fast cyclic convolution algorithm, which is hardware efficient and suitable for high-speed VLSI implementation, especially when the convolution length is large. For example, when the proposed fast cyclic convolution algorithm is applied to the implementation of prime length discrete cosine transform (DCT), the proposed high-throughput implementation of 1297-length DCT design saves 1216 (94%) multiplications, 282 (22%) additions, and 4792 (74%) delay elements compared with those of recently proposed systolic array based algorithms. Furthermore, the proposed algorithm can run at a speed that is 1.5 times that of previous designs and requires less I/O cost as long as the wordlength L is less than 20 bitsKeywords
This publication has 14 references indexed in Scilit:
- A memory-efficient realization of cyclic convolution and its application to discrete cosine transformIEEE Transactions on Circuits and Systems for Video Technology, 2005
- Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short ConvolutionIEEE Transactions on Circuits and Systems I: Regular Papers, 2004
- A systolic array architecture for the discrete sine transformIEEE Transactions on Signal Processing, 2002
- Hardware-efficient DFT designs with cyclic convolution and subexpression sharingIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000
- The efficient memory-based VLSI array designs for DFT and DCTIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
- Algorithm for p/sup m/-length discrete cosine transform1991
- A new systolic array algorithm for discrete Fourier transform1991
- Fast Fourier Transform and Convolution Algorithms1982
- Why systolic architectures?Computer, 1982
- A prime factor FFT algorithm using high-speed convolutionIEEE Transactions on Acoustics, Speech, and Signal Processing, 1977