22.2 A 700MHZ-BW −164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving <-85dBFS HD3 using Digital Cancellation of DAC Errors

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Abstract
High-performance instrumentation and communications demand an ADC technology push to achieve both – an ultra-low NSD of -164dBFS/Hz and HD 3 /IM 3 <−80dBFS – over a BW >500MHz with sub-Watt power dissipation. 3 rd -order distortion matters since for modulated inputs it falls near the signal and limits EVM. Combined with ultra-low NSD, it ensures robustness to large interferers when detecting small signals. Pushing DT ADCs to such performance via impedance scaling imposes significant overhead in the driver and antialiasing filter (AAF). E.g. [1] would need to be ~25×-parallelized to reach the NSD (but would still violate HD 3 ), requiring a large ~27pF load to be driven at 900MHz BW with low NSD, HD 3 , and kickback. AAF design, too, is not easy due to tradeoffs between order, insertion loss, and group delay. CT ΔΣ ADCs are more system-friendly since their resistive input impedance (Z in ) and implicit antialiasing (AA) relax the driver and AAF. However, a single-loop CT ΔΣ ADC requires an OSR>16 to be energy efficient. For BW >500MHz, this translates to a very high f s and, consequently, high power dissipation.