Fast Asynchronous Shift Register for Bit-Serial Communication

This publication has 17 references indexed in Scilit:

• Optimization techniques for FPGA-based wave-pipelined DSP blocks
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
• Adaptive network-on-chip with wave-front train serialization scheme
  2005
• Long wires and asynchronous control
  2004
• Data synchronization issues in GALS SoCs
  2004
• Analog micropipeline rings for high precision timing
  2004
• A 4 Gsamples/s line-receiver in 0.8 μm CMOS
  2002
• Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
  2001
• Wave-pipelining: a tutorial and research survey
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998
• Phased logic: supporting the synchronous design paradigm with delay-insensitive circuitry
  IEEE Transactions on Computers, 1996
• High speed CMOS chip to chip communication circuit
  1991