An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm
- 30 September 2003
- book chapter
- Published by Springer Nature
- p. 292-302
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- AES Implementation on FPGA: Time - Flexibility Tradeoff2002
- Unlocking the design secrets of a 2.29 Gb/s Rijndael processorProceedings of the 39th conference on Design automation - DAC '02, 2002
- An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalistsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001