High-performance 5.2 GHz LNA with on-chip inductorto provide ESD protection
Authors:
- 29 March 2001
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 37 (7) , 467-469
Abstract
A new ESD protection methodology for high-frequency CMOS LNAs is introduced. An on-chip inductor is employed to drain off the hazardous ESD charge while tuning out the harmful parasitic input capacitance. A 5.2 GHz LNA has been designed, attaining high RF performance while providing a high level of ESD protection.Keywords
This publication has 1 reference indexed in Scilit:
- MOS noise performance under impedance matchingconstraintsElectronics Letters, 1999