A 240GHz wideband QPSK receiver in 65nm CMOS
Authors:
- 1 June 2014
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 357-360
Abstract
This paper demonstrates a 240GHz wideband QPSK receiver in 65nm bulk CMOS. A direct-conversion mixer-first architecture is implemented with a 240GHz on-chip antenna. Wideband passive mixers at the front end employ a 240GHz LO and convert the received signal down to baseband. The baseband signal is then amplified using high gain, wide bandwidth amplifiers. The 240GHz LO chain consists of 27GHz/80GHz injection-locked oscillators, 80GHz amplifiers and a frequency tripler. The overall receiver gain is 25dB and the noise figure is 15dB from measurements. This receiver design achieves a data rate of 16Gbps with a power consumption of 260mW.Keywords
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