This study assesses the use of selective LPCVD tungsten as a contact barrier in VLSI circuits. Measurements of the contact resistance and leakage current are evaluated as a function of variations in W deposition parameters, implant type, implant dosage, and metallization heat‐treatment. Addition of to alter the equilibrium of the displacement reaction is seen to cause minimal erosion and encroachment of the Si contacts as well as produce low and thermally stable contact resistances to both n+ and p+ diffusions. For surface doping concentrations of and , measured values of the contact resistance for 2.0 μm sized vias are near 30Ω. Such values are quite compatible with high performance CMOS device requirements. Further reductions in these values are achieved with use of a self‐aligned contact barrier metallization. The contact resistance for 2.0 μm sized vias are, in this case, near 4 and 15OHgr; for the n+ and p+diffusions, respectively. Sporadic leakage across shallow n+/P‐Tub junctions remains, however, a serious problem associated with this selective LPCVD W process. Understanding the origin of this leakage and eliminating it can lead to numerous applications of this technology in VLSI manufacturing.