Architecture Considerations for Stochastic Computing Accelerators

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Abstract
Stochastic computing (SC) is an alternative computing technique for embedded systems which offers lower area and power, and better error resilience compared to binary-encoded (BE) computation. However, the potential of and general design methodologies for SC in accelerator architectures are not well-understood. In this paper, we evaluate individual SC operations, and end-to-end accelerator architectures to understand when and why SC accelerators can achieve compelling energy efficiency gains. Based on these results, we present general design guidelines that should be considered when building energy-optimal SC accelerator architectures. We also evaluate a fully fabricated ASIC prototype—the first of its kind—to empirically evaluate the error tolerance limits of voltage overscaling (VOS) in SC. Our results show that energy efficiency gains from SC primarily stem from SC’s simpler datapaths which require fewer sequential elements compared to BE equivalents. This allows them to achieve energy efficiency gains as high as $2.4 \times $ and $30 \times $ at 8-bit and 4-bit fixed-point precision, respectively. We also find that VOS can improve the energy efficiency further by up to $1.9\times $ by exploiting SC’s error tolerant encoding.
Funding Information
  • Qualcomm
  • National Science Foundation (1518703)

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