High-$Q$ Backside Silicon-Embedded Inductor for Power Applications in $\mu\hbox{H}$ and MHz Range

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Abstract
In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 μH is achieved with an effective inductance density of 0.6 μH/mm 2 . For the 4.5 mm × 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 μH, a dc resistance of 0.6-1.4 Ω , and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics.

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