A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS

Authors:

1 February 2009

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 392-393,393a
DOI:10.1109/isscc.2009.4977473

Abstract

This paper presents a 2.2 GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.

Keywords

PHASE LOCKED LOOPS
PHASE NOISE
JITTER
FREQUENCY LOCKED LOOPS
VOLTAGE-CONTROLLED OSCILLATORS
CLOCKS
SAMPLING METHODS
SPACE VECTOR PULSE WIDTH MODULATION
FREQUENCY SYNTHESIZERS
CAPACITORS

This publication has 1 reference indexed in Scilit:

A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
IEEE Journal of Solid-State Circuits, 2008