A High‐On/Off‐Ratio Floating‐Gate Memristor Array on a Flexible Substrate via CVD‐Grown Large‐Area 2D Layer Stacking
- 26 September 2017
- journal article
- research article
- Published by Wiley in Advanced Materials
- Vol. 29 (44)
Abstract
Memristors such as phase‐change memory and resistive memory have been proposed to emulate the synaptic activities in neuromorphic systems. However, the low reliability of these types of memories is their biggest challenge for commercialization. Here, a highly reliable memristor array using floating‐gate memory operated by two terminals (source and drain) using van der Waals layered materials is demonstrated. Centimeter‐scale samples (1.5 cm × 1.5 cm) of MoS2 as a channel and graphene as a trap layer grown by chemical vapor deposition (CVD) are used for array fabrication with Al2O3 as the tunneling barrier. With regard to the memory characteristics, 93% of the devices exhibit an on/off ratio of over 103 with an average ratio of 104. The high on/off ratio and reliable endurance in the devices allow stable 6‐level memory applications. The devices also exhibit excellent memory durability over 8000 cycles with a negligible shift in the threshold voltage and on‐current, which is a significant improvement over other types of memristors. In addition, the devices can be strained up to 1% by fabricating on a flexible substrate. This demonstration opens a practical route for next‐generation electronics with CVD‐grown van der Waals layered materials.Keywords
Funding Information
- National Research Foundation of Korea (NRF-2015R1C1A1A02037387)
- Ministry of Science, ICT and Future Planning
- Ministry of Trade, Industry and Energy (10064078)
- International Biometric Society (IBS-R011-D1)
This publication has 25 references indexed in Scilit:
- Short-term plasticity and long-term potentiation mimicked in single inorganic synapsesNature Materials, 2011
- Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired ComputingNano Letters, 2011
- Phase Change MemoryProceedings of the IEEE, 2010
- Nanoscale Memristor Device as Synapse in Neuromorphic SystemsNano Letters, 2010
- Synaptic Dynamics in Analog VLSINeural Computation, 2007
- A VLSI Array of Low-Power Spiking Neurons and Bistable Synapses With Spike-Timing Dependent PlasticityIEEE Transactions on Neural Networks, 2006
- Low-cost and nanoscale non-volatile memory concept for future silicon chipsNature Materials, 2005
- A single-transistor silicon synapseIEEE Transactions on Electron Devices, 1996
- Reversible Electrical Switching Phenomena in Disordered StructuresPhysical Review Letters, 1968
- A Floating Gate and Its Application to Memory DevicesBell System Technical Journal, 1967