FPGA implementation and performance evaluation of a high throughput crypto coprocessor
Authors:
- Mostafa I. SolimanMSMostafa I. Soliman
- Ghada Y. AbozaidGAGhada Y. Abozaid
- 1 August 2011
- journal article
- Published by Elsevier in Journal of Parallel and Distributed Computing
- Vol. 71 (8) , 1075-1084
Abstract
No abstract availableKeywords
This publication has 23 references indexed in Scilit:
- Design of a parallel AES for graphics hardware using the CUDA framework2009
- FPGA Implementation(s) of a Scalable Encryption AlgorithmIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
- Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processorsIEEE Transactions on Computers, 2006
- A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology2005
- Architectural design features of a programmable high throughput AES coprocessor2004
- A fully pipelined memoryless 17.8 Gbps AES-128 encryptor2003
- Hardware/compiler codevelopment for an embedded media processorProceedings of the IEEE, 2001
- High Performance Single-Chip FPGA Rijndael Algorithm Implementations2001
- The future of wiresProceedings of the IEEE, 2001
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992