COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits
Authors:
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 568-574
Abstract
The problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits is considered. In addition, it is proposed that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, the problem of generating small and comprehensive test sets is addressed by considering the CMOS stuck-open and the single transition fault models together. A dynamic test compaction technique for two-pattern tests is proposed. The technique exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. Experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits are presented to illustrate the efficacy of the proposed test compaction technique.<>Keywords
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