Effect of extreme surface roughness on the electrical characteristics of ultra-thin gate oxides
Authors:
- 31 January 1999
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 43 (1) , 159-167
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?1998
- Dependence on gate work function of oxide charging, defect generation, and hole currents in metal–oxide–semiconductor structuresJournal of Applied Physics, 1997
- Effect of silicon substrate microroughness on gate oxide qualityJournal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 1996
- Determination of tunnelling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structuresSolid-State Electronics, 1995
- Wear-out of ultra-thin gate oxides during high-field electron tunnellingSemiconductor Science and Technology, 1995
- Characterization of silicon surface microroughness and tunneling transport through ultrathin gate oxideJournal of Vacuum Science & Technology A, 1994
- Atomic-Order Planarization of Ultrathin SiO2/Si(001) InterfacesJapanese Journal of Applied Physics, 1994
- Modeling and characterization of gate oxide reliabilityIEEE Transactions on Electron Devices, 1988
- On the Si-SiO2 interface roughness in VLSI-MOS structuresPhysica Status Solidi (a), 1988
- On tunneling in metal-oxide-silicon structuresJournal of Applied Physics, 1982