Closed-Loop Learning-Based PID Tuning for DC Motor Actuators Using Experimental Data
Authors:
- Jorge A. LizarragaJorge A. Lizarraga
- Luis F. Luque-VegaLuis F. Luque-Vega
- Javier Ruiz-LeonJRJavier Ruiz-Leon
- Rocío Carrasco-NavarroRCRocío Carrasco-Navarro
- Marcela E. Mata-RomeroMMMarcela E. Mata-Romero
- Jesús Antonio Nava-PintorJNJesús Antonio Nava-Pintor
- Fabián García-VázquezFabián García-Vázquez
- Luis O. Solís-SánchezLSLuis O. Solís-Sánchez
- Héctor A. Guerrero-OsunaHéctor A. Guerrero-Osuna
Open Access
Abstract
This paper addresses experimental PID tuning for DC motor actuators when an accurate plant model is unavailable or impractical to obtain. Controller tuning is formulated as a constrained closed-loop optimization process in which each PID gain set is deployed on the physical system, produces an experimental dataset, and is evaluated through a performance index. The objective function combines tracking error, control effort, and control-signal variation, while penalty terms identify and penalize actuator saturation, excessive overshoot, settling-time violations, steady-state error, and divergent responses. Candidate controllers are generated using a constrained Gaussian Cross-Entropy Method and evaluated directly on the physical actuator. The proposed host-embedded architecture separates two computational time scales: PID execution, encoder processing, and data acquisition are performed in real time on the embedded platform, whereas population sampling, candidate ranking, and distribution updates are executed on the host computer between experiments. Within the reported experimental campaign, the sampling distribution progressively concentrates toward gain regions associated with lower closed-loop cost under the prescribed admissibility criteria. The resulting framework provides a structured and traceable procedure for physical controller deployment, data acquisition, constrained performance evaluation, and episodic PID retuning without explicit plant identification. The reported results demonstrate the feasibility of the architecture on the considered platform, without implying comparative superiority, run-to-run statistical convergence, or analytical closed-loop stability.Keywords
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