One of the emerging technologies, which is distinguished by its small size and low power devices, is Single Electron Technology (SET). In this paper, efficient single-electron logic circuits and memory elements are proposed for nanotechnology. These circuits, including new minority-based NAND and NOR universal gates as well as R-S latch, D latch and D flip-flop memory elements, are designed based on a new method, using SET-based static inverters. This method of design reduces the number of circuit elements and decreases the complexity of the designed circuits. Furthermore, by utilizing this method the commonly used architectures can be implemented efficiently in SET technology. The functionality of the proposed circuits has been verified using SIMulation Of Nanostructure (SIMON) package. The proposed designs also outperform the most prominent stateof-the-art circuits in terms of the circuit element count, the critical path delay and the switching energy consumption.