Area-optimized design of SOT-MRAM

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Abstract
In this letter, we present a new structure of spin-orbit torque magnetic random access memory (SOT-MRAM) for area optimization. Based on the observation of SOT-MRAM layout that the metal line can be added in the horizontal direction without increasing the cell area, the proposed design optimizes the metal line routing direction as well as biasing conditions for read and write operations. Implemented with a 45-nm CMOS technology, the proposed design achieves cell area reduction of 42% (23%) compared with the conventional SOT-MRAM (STT-MRAM). The proposed design achieves 6.26x lower write power than STT-MRAM by taking advantage of high spin current injection efficiency. Also, owing to separate read and write current paths, the proposed design can optimize each path independently, resulting in 7.69x lower read power and 1.88x higher read-disturb margin in comparison to STT-MRAM that has a common path for read and write operations.

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