40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology
Authors:
- 30 November 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 39 (12) , 2389-2396
Abstract
A triple-resonance LC network increases the bandwidth of cascaded differential pairs by a factor of 2/spl radic/3, yielding a 40-Gb/s CMOS amplifier with a gain of 15 dB and a power dissipation of 190 mW from a 2.2-V supply. An ESD protection circuit employs negative capacitance along with T-coils and pn junctions to operate at 40 Gb/s while tolerating 700-800 V.Keywords
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