Temperature dependences of threshold voltage and drain-induced barrier lowering in 60nm gate length MOS transistors

This publication has 17 references indexed in Scilit:

• Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities
  Microelectronics Reliability, 2012
• Subthreshold Characteristics of MOS Transistors With $ \hbox{CeO}_{2}/\hbox{La}_{2}\hbox{O}_{3}$ Stacked Gate Dielectric
  IEEE Electron Device Letters, 2011
• On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors
  Microelectronic Engineering, 2006
• Low field electron mobility in ultra-thin SOI MOSFETs: experimental characterization and theoretical investigation
  Solid-State Electronics, 2004
• Defects in silicon oxynitride gate dielectric films
  Microelectronics Reliability, 2002
• FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
  IEEE Transactions on Electron Devices, 2000
• Study of thin gate dielectric films using deep level transient spectroscopy
  Microelectronics Journal, 2000
• CMOS scaling into the nanometer regime
  Proceedings of the IEEE, 1997
• DIBL in short-channel NMOS devices at 77 K
  IEEE Transactions on Electron Devices, 1992
• MOS device modeling at 77 K
  IEEE Transactions on Electron Devices, 1989