Programmable multimedia platform based on reconfigurable processor for 8K UHD TV

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Abstract
This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K (7680 × 4320) Ultra High Definition (UHD) TV that operates at a maximum rate of 60 frames per second. To support the massive computational load and memory bandwidth of 8K video, several key features have been implemented in the proposed platform such as symmetric multi-cluster architecture for data partitioning, a ring-data path between the clusters to support data pipelining, on-the-fly processing architecture for the reduction of the DDR bandwidth, and flexible hardware accelerators that facilitate the computation of common kernels by video-qualityenhancement algorithms. In addition, within a context of continuously evolving and changing UHD-TV video algorithms, system flexibility is crucial to support new algorithms and enhance competitiveness. The programmability of the main core of the proposed platform the reconfigurable processor (RP) makes it possible to upgrade the algorithms even after the hardware design is fixed. The proposed platform was embedded into the System on Chip (SoC), and a new 8K UHD-TV model that features this programmable solution is expected to appear on the market in the near future.

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