Metastablility in SAR ADCs

Authors:

Vol. 64 (2) , 111-115
DOI:10.1109/tcsii.2016.2554798

Abstract

The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion scheme, which includes the regeneration and the reset process of the comparator in a feedback loop, thus significantly reducing the available time for the regeneration. Our analysis considers the probability of metastability errors as a function of their magnitude and is customized for a timer-based asynchronous SAR ADC (with loop time-out). The resulting framework can also quantify the metastability in a synchronous architecture, and we provide a numerical comparison. To validate the analysis, measurement results of an 8-bit 130-MS/s SAR ADC in 90-nm CMOS are provided.

Keywords

Funding Information

Research Committee of University of Macau
Macao Science and Technology Development Fund (SKL/AMS-VLSI/SSW/13-Y3/FST, FDCT/053/2014/A1)

This publication has 7 references indexed in Scilit:

Analysis of Metastability in Pipelined ADCs
IEEE Journal of Solid-State Circuits, 2014
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
IEEE Journal of Solid-State Circuits, 2013
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
IEEE Journal of Solid-State Circuits, 2010
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
IEEE Journal of Solid-State Circuits, 2006
Power-efficient metastability error reduction in CMOS flash A/D converters
IEEE Journal of Solid-State Circuits, 1996
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC
IEEE Journal of Solid-State Circuits, 1995
A 400-MHz input flash converter with error correction
IEEE Journal of Solid-State Circuits, 1990