Design and Development of Polarization-Enhanced E-Mode GaN p-FET and Complementary Logic (CL) Circuits

Authors:
Publisher website
Google Scholar
Abstract
The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (tx) is found to be a critical parameter that influences the device metrics. With a decrease in tx (i.e., larger recess depth), a more negative threshold voltage (Vth) is achieved; however, the trade-off is an increase in $\textit{R}_{\biosc{on}}$. The E-mode GaN p-FET with tx = 32 nm exhibits a Vth of -1.1 V, a high current density of 17.7 mA/mm, a high $\textit{I}_{\biosc{on}}$/$\textit{I}_{\biosc{off}}$ of 6.9 × 107, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a Vth of 1.3 V and an $\textit{R}_{\biosc{on}}$ of 6 Ω⋅mm. Finally, a GaN CL inverter was fabricated and demonstrated under VDD = 6 V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).
Funding Information
  • National Key Research and Development Program of China (2022YFB3604400)

This publication has 44 references indexed in Scilit: