Parallel Slew-Rate Enhancer With Current-Recycling Core for Switched-Capacitors Circuits

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Abstract
Enhancing the slew-rate and settling speed of amplifiers in switched-capacitor circuits without incurring in static power penalties has long been a focal point. Standardized solutions remain elusive due to significant design challenges, particularly when confronted with capacitive loads close to the range of internal parasitic capacitances. Herein, we present a novel parallel-type slew-rate enhancer based on a current-recycling core, along with insights regarding settling time optimization under power constraints. We designed a switched-capacitor integrator based on a recycling folded cascode OTA, assisted by the proposed slew-rate enhancer, in a 180-nm 1.8-V CMOS technology. The circuit is operated with an equivalent capacitive load of approximately 8 pF and an input differential voltage step as large as 3.6 V. The system is required to settle in less than 40 ns, with a relative error on the final value below 0.1%. Simulation results show that, within the power budget of 540 μ W, the proposed solution achieves a × 3.5 improvement in settling time compared to the OTA alone and a × 2.1 improvement compared to the OTA assisted by a standard parallel slew-rate enhancer.
Funding Information
  • NRRP of Italian MIUR
  • EU-NextGenerationEU through the Project HeMoWear (0004610/2022)

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