A 0.13 µm 8 Mb Logic-Based Cu$_{\rm x}$Si$_{\rm y}$O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

A 0.13 µm 8 Mb ${\rm Cu}_{\rm x}{\rm Si}_{\rm y}{\rm O}$ resistive random access memory (ReRAM) test macro with $20{\rm F}^{2}$ cell size is developed based on logic process for embedded applications. Smart and adaptive write and read assist circuits are proposed to fix yield and power consumption issues arising from large variations in set/reset time and high-temperature cell resistance. Self-adaptive write mode (SAWM) helps increase the ${\rm R}_{\rm off}/{\rm R}_{\rm on}$ window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and the high power consumption is eliminated after the cell switches to ${\rm R}_{\rm on}$ during set. Self-adaptive read mode (SARM) increases read bit yield from 98% to 100% at 125 $^{\circ}{\rm C}$ . The typical access time of the on-pitch voltage sense amplifier (SA) is 21 ns. High bandwidth throughput is supported.