Differential pass transistor logic in CMOS technology

Authors:

13 March 1986

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 22 (6) , 294-295
DOI:10.1049/el:19860200

Abstract

Differential pass transistor logic is described in the letter. This configuration results in better silicon area efficiency and higher speed of operation than conventional CMOS pass transistor logic.

Keywords

CLOCKED BUFFERS
SI AREA EFFICIENCY
CONFIGURATION
CMOS DIFFERENTIAL PASS TRANSISTOR LOGIC
OPERATION SPEED